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EUA4890 1 Watt Audio Power Amplifier
DESCRIPTION
The EUA4890 is an audio power amplifier designed for portable communication device applications such as mobile phone applications. The EUA4890 is capable of delivering 1.0W of continuous average power to an 8 BTL and with less than 1% distortion (THD+N) from a 5.0V power supply, and 350mW to a 8 BTL load from a 3V power supply. The EUA4890 provides high quality audio while requiring few external components and minimal power consumption. It features a low-power shutdown mode, which is achieved by driving the SHUTDOWN pin with logic low. The EUA4890 contains circuitry to prevent from "pop and click" noise that would otherwise occur during turn-on and turn-off transitions. For maximum flexibility, the EUA4890 provides an externally controlled gain (with resistors), as well as an externally controlled turn-on and turn-off times (with the bypass capacitor). The EUA4890 is available in a MSOP-8 , 3mmN 3mm DFN package.
FEATURES
2.5-5.5V operation 65dB PSRR at 217Hz, VDD=5V 0.1A ultra low current shutdown mode Improved pop & click circuitry No output coupling capacitors, snubber networks or bootstrap capacitors required Thermal shutdown protection Unity-gain stable External gain configuration capability BTL output can drive capacitive loads
RoHS compliant and 100% lead(Pb)-free
APPLICATIONS
Mobile Phones PDAs Portable electronic devices
Block Diagram
Figure1.
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EUA4890
Typical Application Circuit
Figure2. Audio Amplifier with Single -Ended Input
Figure3. Audio Amplifier with Differential Input
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Pin Configurations
Package Type Pin Configurations Package Type Pin Configurations
Top View
Top View
MSOP-8
DFN-8
Pin Description
PIN PIN I/O DESCRIPTION
SHUTDOWN BYPASS +IN -IN VO1 VDD GND VO2
1 2 3 4 5 6 7 8
I I I I O I
The device enters in shutdown mode when a low level is applied on this pin Bypass capacitor pin which provides the common mode voltage Positive input of the first amplifier, receives the common mode voltage Negative input of the first amplifier, receives the audio input signal. Connected to the feedback resistor Rf and to the input resistor Rin. Negative output of the EUA4890. Connected to the load and to the feedback resistor Rf Analog VDD input supply. Ground connection for circuitry.
O
Positive output of the EUA4890.
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Ordering Information
Order Number Package Type Marking Operating Temperature range
EUA4890MIR1 EUA4890JIR1
MSOP-8 DFN-8
xxxx A4890 xxxx A4890
-40 C to 85C -40 C to 85C
EUA4890
1/4
1/4
1/4
1/4
Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: DFN M: MSOP
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Absolute Maximum Ratings
u
Supply voltage, VDD
u u
--------------------------------------------------------------------------------------------
6V
Input voltage, VI ---------------------------------------------------------------------------u
-0.3 V to VDD +0.3V -65C to 150C 2kV 150C
Storage temperature rang, Tstg ------------------------------------------------------------------ESD Susceptibility
u
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Junction Temperature
u
Thermal Resistance JC (MSOP) ---------------------------------------------------------------------------------------------
56C/W JA (MSOP) ---------------------------------------------------------------------------------------------- 160C/W JA (DFN) ---------------------------------------------------------------------------------------------- 50C/W
Electrical Characteristics VDD = 5V, TA = 25C Symbol
IDD ISD VSDIH VSDIL VOS
Parameter
Quiescent Power Supply Current Shutdown Current Shutdown Voltage Input High Shutdown Voltage Input Low Output Offset Voltage
Conditions
VIN=0V, IO=0A, No load VIN=0V, IO=0A, 8 load VSHUTDOWN=0V
Min
EUA4890 Typ Max.
2.4 2.5 0.1 5 5 2.0
Unit
mA mA A V
1.2 0.4 5 7.0 THD=1%; f=1kHz 8.5 1.1 170 150 PO=0.4 Wrms; f=1kHz Vripple=200mV sine p-p Input Terminated with 10 ohms to ground 8 load 55 170 0.15 65(f=217 Hz) 67(f=1kH z) 1.0 220 25 9.7
V mV k W ms C % dB ms
ROUT-GND Resistor Output to GND PO TWU TSD Output Power (8) Wake-up time Thermal Shutdown Temperature
THD+N Total Harmonic Distortion + Noise PSRR TSDT Power Supply Rejection Ratio Shutdown Time
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Electrical Characteristics VDD = 3V, TA = 25C Symbol
IDD ISD VSDIH VSDIL VOS
Parameter
Quiescent Power Supply Current Shutdown Current Shutdown Voltage Input High Shutdown Voltage Input Low Output Offset Voltage
Conditions
VIN=0V, IO=0A, No load VIN=0V, IO=0A, 8 load VSHUTDOWN=0V
Min
EUA4890 Typ Max.
1.8 1.9 0.1 4 4 2.0
Unit
mA mA A V
1.2 5 7.0 THD=1%; f=1kHz 0.28 150 PO=0.15 Wrms; f=1kHz Vripple=200mV sine p-p Input Terminated with 10 ohms to ground 45 8.5 0.35 120 170 0.15 65(f=217 Hz) 66(f=1kH z) 0.4 25 9.7 180
V mV k W ms C % dB
ROUT-GND Resistor Output to GND PO TWU TSD Output Power (8) Wake-up time Thermal Shutdown Temperature
THD+N Total Harmonic Distortion + Noise PSRR Power Supply Rejection Ratio
Electrical Characteristics VDD = 2.6V, TA = 25C Symbol
IDD ISD PO
Parameter
Quiescent Power Supply Current Shutdown Current Output Power (8) Output Power (4)
Conditions
VIN=0V, IO=0A, No load VSHUTDOWN=0V THD=1%; f=1kHz THD=1%; f=1kHz PO=0.1Wrms; f=1kHz Vripple=200mV sine p-p Input Terminated with 10 ohms to ground
Min
EUA4890 Typ Max.
1.7 0.1 0.25 0.32 0.15 55(f=217 Hz) 56(f=1kH z)
Unit
mA A W % dB
THD+N Total Harmonic Distortion + Noise PSRR Power Supply Rejection Ratio
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Typical Operating Characteristics
Figure3.
Figure4.
Figure5.
Figure6.
Figure7.
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Figure8.
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Figure9.
Figure10.
Figure11.
Figure12.
Figure13.
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Figure14.
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Figure15.
Figure16.
Figure17.
Figue18.
Figure19.
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Figure20.
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Figure21.
Figure22.
Figure23.
Figure24.
Figure25.
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Figure26.
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Figure27.
Figure28.
Figure29.
Figure30.
Figure31.
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Application Information
Bridged Configuration Explanation
The structure of the EUA4890 is basically composed of two identical internal power amplifiers; the first one si externally configurable with gain-setting resistors Rin and Rf (the closed-loop gain is fixed by the ratios of theses resistors) and the second is internally fixed in an inverting unity-gain configuration by two resistors of 20k. So the load is driven differentially through OUTA and OUTB outputs. This configuration eliminates the need for an output coupling capacitor. The differential-ended amplifier presents two major advantages: - The possible output power is four times larger (the output swing is doubled) as compared to single-ended amplifier under the same conditions. - Output pins (OUTA and OUTB) are biased at the same potential VDD/2, this eliminates the need for an output coupling capacitor required with a single-ended amplifier configuration. The differential closed loop-gain of the amplifier is given by Avd=
2x f = Vorms R Vinrms in R
Power Dissipation Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Since the EUA4890 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation for a given application can be derived from the power dissipation graphs of from equation1.
Proper Selection of External Components The EUA4890 is unity-gain stable and requires no external components besides gain-setting resistors, and input coupling capacitor and proper bypassing capacitor in the typical application. Gain-Setting Resistor Selection (Rin and Rf) Rin and Rf set the closed-loop gain of the amplifier. In order to optimize device and system performance, the EUA4890 should be used in low gain configurations. The low gain configuration minimizes THD + noise values and maximizes the signal to noise ratio, and the amplifier can still be used without running into the bandwidth limitations. Low gain configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1Vrms are available from sources such as audio codecs. A closed loop gain in the range from 2 to 5 is recommended to optimize overall system performance. An input resistor (Rin) value of 20k is realistic in most of applications, and does not require the use of a too large capacitor Cin. Input Capacitor Selection (Cin) The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high-pass filter with Rin, the cut-off frequency is given by
fc = 1 2 * *R in *C in
PDMAX = 4 * (VDD ) 2 /(2 2 R L ) ------------(1)
It is critical that the maximum junction temperature TJMAX of 150C is not exceeded. TJMAX can be determine from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the thermal resistance of the application can be reduced, resulting in higher PDMAX. Additional copper foil can be added to any of the leads connected to the EUA4890.If TJMAX still exceeds 150C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power.
The size of the capacitor must be large enough to couple in low frequencies without severe attenuation. However a large input coupling capacitor requires more time to reach its quiescent DC voltage (VDD/2) and can increase the turn-on pops. An input capacitor value between 0.1 and 0.39F performs well in many applications (with Rin=22k). Bypass Capacitor Selection (Cby) The bypass capacitor Cby provides half-supply filtering and determines how fast the EUA4890 turns on. This capacitor is critical component to minimize the turn-on pop. A 1.0F bypass capacitor value (Cin=O 0.39F) should produce clickless and popless shutdown transitions. The amplifier is still functional with a 0.1F capacitor value but is more susceptible to pop and click noise. Thus, a 1.0F bypassing capacitor is recommended. Power Supply Bypassing (CS) As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device is possible.
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Packaging Information
MSOP-8
SYMBOLS A A1 D E1 E L b e
MILLIMETERS MIN. MAX. 1.10 0.00 0.15 3.00 3.00 4.70 5.10 0.40 0.80 0.22 0.38 0.65
INCHES MIN. 0.000 0.118 0.118 0.185 0.016 0.008 0.026 0.201 0.031 0.015 MAX. 0.043 0.006
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DFN-8
SYMBOLS A A1 b D D1 E E1 e L
MILLIMETERS MIN. MAX. 0.70 0.90 0.00 0.05 0.20 0.40 2.85 3.15 2.30 2.85 3.15 1.50 0.65 0.25 0.45
INCHES MIN. 0.028 0.000 0.008 0.112 0.090 0.112 0.059 0.026 0.010 0.018 0.124 MAX. 0.035 0.002 0.016 0.124
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